Hardware acceleration is widely applied to the field of computers, the telecommunications field, and the like. Currently, Microsoft has deployed a field programmable gate array (FPGA) in a data center, to accelerate Bing search. As shown in FIG. 1, one peripheral component interconnect express (PCIe) card is disposed on each server, to connect central processing units (CPU) and FPGAs. The FPGAs are connected by using a separate network, to form an FPGA array network. The plurality of FPGAs jointly finish acceleration of an application such as searching and deep learning, and a data forwarding port between a plurality of FPGAs implementing acceleration of one application is designated by a corresponding CPU. Specifically, after a server of a data center receives a search request, the server analyzes content of the search request, divides a search task into a plurality of operations such as keyword extraction of web page searching, matching of a free expression, and grading, and distributes tasks corresponding to the operations to FPGAs. After performing the operations, the FPGAs return results to respective CPUs, and the CPUs send the results to a CPU initiating the request, so that the CPU aggregates the results. In the acceleration solution, an application developer needs to learn in advance an interconnection manner of the FGPAs, and designates a forwarding port of an intermediate result obtained after processing of the FPGAs. Therefore, in an FPGA acceleration network of Microsoft, a routing and forwarding path is designated by one or more CPUs corresponding to each application, and the FPGA network does not have a routing function. In addition, a conventional routing network implements routing from a source node to a unique destination node based on a media access control (MAC) address. For a network including accelerators of a plurality of acceleration types, if only an acceleration sequence is designated but a location of a destination accelerator is not designated, a corresponding packet cannot be routed to a plurality of destination accelerators, to implement application acceleration.